There are a number of well-known basic architectures for volatile MOS random access memory (RAM) cells. These include the conventional dynamic RAM (DRAM) cell that utilizes a storage capacitor and an NMOS transfer device connected to the bit and word lines of the memory array. Conventional static RAM (SRAM) cell architectures include a six-transistor design in which coupled latch invertors are controlled by two NMOS devices connected to the bit and word lines. In a variation of the six-transistor SRAM cell, a four-transistor design is used and the PMOS devices in the coupled latch invertors are replaced by large resistors.
Well-known non-volatile memory cell architectures include electrically programmable read only memory (EPROM) and flash EPROM cells in which a floating gate is used to store information in an NMOS device that is connected directly to the bit and word lines. Non-volatile cells also include two-transistor electrically erasable programmable read only memory (EEPROM) cells in which, in addition to the EPROM device elements, an extra NMOS device is included to interface with the bit and word lines.
Thus, in the conventional memory cell architectures, information storage is based upon either triggering into a new current conducting state, which requires refreshing, or charge storage in a floating gate, which requires a more complex cell.
There are also a number of lesser-utilized memory architectures, such as, for example, ferro-electric, spin valve and molecular memories, that are not directly compatible with CMOS processing.
The present invention provides a new semiconductor memory cell that is based upon the well-known snapback characteristics of the parasitic NPN structure inside an NMOS device. The memory cell is based upon the dynamic storing and reading of information utilizing a short pulse operation mode for both Vds and Vgs. The cell relies upon the dependence of the drain-source triggering voltage upon the previously injected carrier within the P-well of the device. The cell self-refreshes in the “on” state by using periodic drain-source Vds voltage pulses having a width of 0.1–10 ns and a period of 10–100 ns with or without a Vgs hold. The turn-on of the cell is controlled by the gate-source voltage Vgs or the control electrode voltage. The state of the memory cell is read by applying Vgs read and Vds read voltages between the refresh pulses to the corresponding bit and word buses. Individual cells are erased by a short pulse application of the Vgs erase and Vds erase signals to the cell. The entire array is erased by a short pulse application the Vds erase signal to the array.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description of the invention and the accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.